This is achieved by subtracting the sum of two (n + 1)-bit input numbers by the constant 2ⁿ + 1 and producing carry and sum vectors. We propose improved area-efficient weighted modulo 2ⁿ + 1 adder design using diminished-1 adders with simple correction schemes.The modulo 2ⁿ + 1 addition can then be performed using parallel-prefix structure diminished-1 adders by taking in the sum and carry vectors plus the inverted end-around carry with simple correction schemes.
No comments:
Post a Comment