Background

The Residue number system (RNS) has been employed for efficient parallel carry-free arithmetic computations  (addition, subtraction, and multiplication) in DSP  applications  as the computations for each residue channel can  independently be done without carry propagation. Since RNS based computations can achieve significant speed up over the binary-system-based computation, they are widely  used in DSP  processors, FIR filters, and communication  Components.Arithmetic modulo 2ⁿ + 1 computation is one of the most common RNS operations that are used in pseudorandom number generation and cryptography.

8-bit Brent-Kung Adder

The Brent-Kung adder is a parallel prefix adder that requires 2(log2N)-1 stages.It was originally proposed as a simple and regular design of a parallel adder that addresses the problems of connecting gates in a way to minimize chip area. Accordingly, it is considered one of the better tree adders for minimizing wiring tracks, fanout, and gate count and is used as a basis for  any other networks. The operation of parallel prefix adders depends on the notion of group carry propagate and generate signals.In essence, a group of bits generate a carry when its carry is true independent of the carry-in and propagate a carry when its carryout is true when there is carry-in.

Proposed Addition

 For Example: Let n= 4 bit;
                           A=15 = 1111
                           B=14 = 1110            
Proposed Addition: A+B-(2n+1); if A+B> 2n
                                 = 15+ 14- (16+1)
                                 = 12= 1100

Proposed System

This is achieved by subtracting the sum of two (n + 1)-bit input numbers by the constant 2ⁿ + 1 and producing carry and sum vectors. We propose improved area-efficient weighted modulo 2ⁿ + 1 adder   design using diminished-1 adders with simple correction schemes.The modulo 2ⁿ + 1 addition can then be performed using parallel-prefix structure diminished-1 adders by taking in the sum and carry vectors plus the inverted end-around carry with simple correction schemes.
 

Introduction

As one of the processor's ALU performance issues, the carry propagation during the addition operation limits the speed of arithmetic operation. We Propose an improved area-efficient weighted modulo adders. This is achieved by modifying existing diminished-1 modulo  adders to incorporate simple correction schemes.
 We Proposed adders can produce modulo sums within the range {0,2^n }, which is more than the range {0,2^n-1  } produced by existing diminished-1 modulo adders.