Introduction

As one of the processor's ALU performance issues, the carry propagation during the addition operation limits the speed of arithmetic operation. We Propose an improved area-efficient weighted modulo adders. This is achieved by modifying existing diminished-1 modulo  adders to incorporate simple correction schemes.
 We Proposed adders can produce modulo sums within the range {0,2^n }, which is more than the range {0,2^n-1  } produced by existing diminished-1 modulo adders.